Product Summary

The EPM7032STI44-7N high-density, high-performance PLD is based on Altera second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7032STI44-7N family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. EPM7032STI44-7NS devices in the -5, -6, -7, and -10 speed grades as well as EPM7032STI44-7N and EPM7032STI44-7NE devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM7032STI44-7N absolute maximum ratings: (1)VCC Supply voltage With respect to ground: -2.0 to 7.0 V; (2)VI DC input voltage: -2.0 to 7.0 V; (3)IOUT DC output current, per pin: -25 to 25 mA; (4)TSTG Storage temperature No bias: -65 to150 ℃; (5)TAMB Ambient temperature Under bias: -65 to 135 ℃; (6)TJ Junction temperature Ceramic packages, under bias: 150 ℃; (7)PQFP and RQFP packages, under bias: 135 ℃.

Features

EPM7032STI44-7N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices- ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter; (7)frequencies (including interconnect); (8)PCI-compliant devices available.

Diagrams

EPM7032STI44-7N block diagram

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