(China (Mainland))
Product Summary
The CY7C1463AV33-133AXI is a 3.3V, 2M x 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1463AV33-133AXI is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.
Parametrics
CY7C1463AV33-133AXI absolute maximum ratings: (1)Storage Temperature: –65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage on VDD Relative to GND: –0.5V to +4.6V; (4)Supply Voltage on VDDQ Relative to GND: –0.5V to +VDD; (5)DC Voltage Applied to Outputs in Tri-State: –0.5V to VDDQ + 0.5V; (6)DC Input Voltage: –0.5V to VDD + 0.5V; (7)Current into Outputs (LOW): 20 mA; (8)Static Discharge Voltage (MIL-STD-883, Method 3015): >2001V; (9)Latch Up Current: >200 mA.
Features
CY7C1463AV33-133AXI features: (1)No Bus Latency. (NoBL.) architecture eliminates dead cycles between write and read cycles; (2)Supports up to 133 MHz bus operations with zero wait states: Data is transferred on every clock; (3)Pin compatible and functionally equivalent to ZBT devices; (4)Internally self timed output buffer control to eliminate the need; (5)to use OE; (6)Registered inputs for flow through operation; (7)Byte write capability; (8)3.3V and 2.5V IO power supply; (9)Fast clock-to-output times: 6.5 ns (for 133 MHz device); (10)Clock Enable (CEN) pin to enable clock and suspend operation; (11)Synchronous self timed writes; (12)Asynchronous Output Enable; (13)IEEE 1149.1 JTAG-compatible boundary scan; (14)Burst capability: linear or interleaved burst order; (15)Low standby power.
Diagrams
| Image | Part No | Mfg | Description |  |
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 CY7C1463AV33-133AXI |
Cypress Semiconductor |
SRAM 2Mx18 3.3V NoBL-FT SRAM |
Data Sheet |
Negotiable |
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